Ashling to provide RiscFree™ RISC-V Toolchain support for Intel FPGAs

Ashling to provide RiscFree™ RISC-V Toolchain support for Intel FPGAs


DALLAS – (BUSINESS THREAD) –Intel Vision 2022 – Ashling has announced that Ashling’s No Risk Toolchain will provide support for Intel’s FPGAs, including Intel’s Nios V processor later this year.

No risk is Ashling’s integrated development (IDE) environment that includes a compiler and debugger and provides software development and debugging support for Nios V, the next-generation smooth processor for Intel FPGA based on the overall architecture of RISC-V instructions.

Since its introduction, Ashling’s No risk toolchain has been steadily increasing its market share within the embedded tools market and is especially strong in the RISC-V market, where its ease of use, wide functionality and plug-in architecture have made it Preferred option for 32-bit and 64-bit basic RISC software development.

“We are pleased to announce our collaboration with Intel and the inclusion of Ashling’s RiscFree tools as part of Intel’s Nios V processor software development and debugging solution. We believe that the support of our RiscFree Toolchain Market leader will help accelerate the deployment of solutions with Intel’s Nios V processors throughout Intel’s FPGA family. dit Hugh O’Keeffe, CEO of Ashling.

“Intel is pleased to work with Ashling to enable the RiscFree toolkit for our new RISC-V-based Nios V processors,” he said. Deepali Trehan, vice president of Intel’s programmable solutions group. “Nios V opens up a broad open source RISC-V ecosystem, enabling our customers to use their preferred tool chains while saving development time and costs. ”

He RiscFree for Intel FPGA tool chain features include:

  • Project manager and build manager, including Make and CMake support with quick import, build, and debugging of application frameworks created by Intel Quartus

  • The Nios V GCC compiler toolbox is fully integrated into the No Risk IDE with support for newlib or picolibc runtime libraries using the Nios V Hardware Abstraction Layer (HAL) API for hardware access

  • Runtime debugging and real-time tracking with support for Intel FPGA II (USB Blaster II) download cable

  • Zephyr, FreeRTOS, and μC / OS RTOS provide debugging support and awareness

  • Support for custom instructions and extensions for the Nios V processor

Read Intel and Ashling’s joint white paper here and for more details on Intel’s Nios V see here.

About Ashling

Ashling has been a leading provider of integrated development tools and services since 1982 with design centers in Limerick, Ireland and Cochin India, and sales and support offices in Europe, Asia Pacific, the Middle East and the Americas. Visit www.ashling.com for more information.

About RISC-V

The RISC-V Open Architecture ISA is under the government of RISC-V International. Visit https://riscv.org for more details.

Intel, the Intel logo, and other Intel trademarks are trademarks of Intel Corporation or its affiliates.



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